题目

英语翻译
Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset,and comparator delay compensation
Carsten Wulff • Trond Ytterdal
Received:13 March 2010 / Revised:30 November 2010 / Accepted:3 December 2010 / Published online:19 December 2010
2 The Author(s) 2010.This article is published with open access at Springerlink.com
Abstract We present a differential comparator-based
switched-capacitor (CBSC) pipelined analog-to-digital
converter (ADC) with comparator preset,and comparator
delay compensation.Compensating for the comparator
delay by digitally adjusting the comparator threshold
improves the ADC resolution from 2.5-bit to 7.05-bit.The
ADC is manufactured in a 90 nm CMOS technology,with
a core area of 0.85 mm 9 0.35 mm,a 1.2 V supply for the
core and 1.8 V for the input switches.It has an effective
number of bits (ENOB) of 7.05-bit,and a power dissipation
of 8.5 mW at 60 MS/s.提问时间：2021-04-08

答案

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation基于校准器可开关电容管式数码模拟转换器,以及校准器预设和校准器延迟补偿...